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preliminary this is a product that has fixed target specifications but are ramtron international corporation subject to change pending characterization results. 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000 http://www.ramtron.com rev. 1.4 may 2011 page 1 of 32 wm7 2 016 16kbit secure f - ram memor y with gen - 2 rfid access & serial port direct m emory acces s description the wm72016 is a rfid transponder ic with nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory , or f - ram , is nonvolatile and performs reads and writes like a ram. it provide s reliable data retention for 20 years while eliminating the complexities, ov erhead, and system level reliability problems caused by eeprom and other nonvolatile memories. unlike eeprom?s, the wm72016 write operations are z ero p ower C there is no power or speed premium paid for executing writes into the wm72016 as compared to rea d power and speed . operation of the memo ry is fully symmetric: it has an equivalent read and write range. t he wm72016 ?s rfid interface is compatible with the epc class - 1 generation - 2 uhf rfid protocol for communications at 860 mhz C 960 mhz, version 1.2.0 specification for rfid air interface. the wm72016 is a two chip configurat ion offered in various forms: standard ic package or wafer s . all specifications discussed here in are applicable to the combined chipset operation. figure 1. system block diagram features 16 kbit ferroelectric nonvolatile ram ? organized as 1024 x 16 bits ? very high read/write e ndurance (> 10 1 4 ) ? 20 - year data retention ? gamma s tability demonstrated to > 30 kgy ? symmetric read/write o peration ? advanced high - reliability ferroelectric process interface and security features ? epc class 1 gen2 ( iso18000 - 6c ) rfid compatible interface (revision 1.2.0) ? 192 - bit memory: 96 - bit electronic product code? (epc), 32 - bit access p assword, 32 - bit kill password, 64 - bit tid memory (factory programmed and locked) ? inventory, read, write and erase features ? kill c ommand ? block permalock c ommand ? access c ommand ? uhf carrier frequencies from 860 mhz to 960 mhz ism band , ask demodulation ? tag - to - reader link frequencies u p to 640kbps ? reader - to - tag asymptotical transmission rates up to 128kbps ? supports fm0 and mms data encoding formats ? serial port i nterface custom features ? stored address pointer to improve data write speed ? stored address pointer lock ? block write c ommand ? variable user memory block size support ? interrupt g eneration ultra low power operation ? memory read/w rite s ensitivity : < - 6 d b m ( typ. ) industry standard configuration s ? industrial temperature - 40 ? c to +85 ? c ? b umped w afers ? 8 - pin udfn wm72016 rfid tag wit h f - ram rfid reader (class - 1 gen - 2)
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 2 of 32 pin configuration ( u dfn package) top view (pcb layout) 3.0 mm 3.0 mm body, 0.65 mm pad pitch pin description pin name pin number type description a nt+, ant - 7 , 8 i nput rfid antenna. connect to external rfid antenna terminal s . connect ant - to ex ternal rfid antenna terminal, a lso acts as ground. ser_clk 1 i nput serial interface clock ser_dat1, ser_da t 0 2, 3 i/o serial interface bi - directional data ser_cs 4 i/o serial interface bi - directional chip select/interrupt vddraw 5 pwr power supply input pin. dc supply (2.1v to 3.0v) vddr 6 pwr power supply output pin. this supply is int erna lly generated via the rf field . the vddr and vddraw pins are tied together for most applications. contact the factory for other applications such as battery assisted systems . 8 7 6 5 1 2 3 4 s e r _ c l k s e r _ d a t 1 s e r _ d a t 0 s e r _ c s a n t - a n t + v d d r v d d r a w
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 3 of 32 f unctional descriptio n the wm72016 is a non - volatile memory device with an industry standard uhf rfid interface that enables processing data in and out of memory as a generic passive rfid transponder. unlike ot her transponder ic s, the wm72016 transponder ic contains high density symmetric read/write f - ram memory that enables unique applications of an rfid solution. when combined with an appr opriate antenna design, wm72016 will power up with energy harvested directly from the rf field. following an internally generated reset state, the ic configures itself according to pre - programmed configuration settings that were stored in f - ram non - volati le memory at wafer probe, packaged parts test, or end unit transponder personalization at end - user depot. configuration settings are read out of memory and applied prior to enabling data transmission in or out of memory. as specified in the gen2 standard, the chip receives and processes commands transmitted by the rfid interrogator (reader). all required and most optional commands are supported. in addition to these, wm72016 supports a number of custom commands that take advantage of f - ram?s unique ultra low power and symmetrical characteristics. referring to figure 2 , the transponder ic?s consist of an rfid interface, c ontrol and authentication logic, f - ram memory, and power management unit. the external antenna is connected directly to the rfid interface where the rf signal is rectified with high efficiency schottky diode based rectifier. the rectified voltage is multiplied up within the schottky array and then regulated to supply power to on - chip resources. also included in the rfid interface is a modulator/demodulator that detects incoming signals and modulates the input impedance to enable backscattering of returned signal s. the control and authentication logic processes commands to enable access in and out of f - ram memory. figure 2. block diagram power management rfid interface control and authentication logic f - ram array (16kb) external mcu (optional)
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 4 of 32 memory map wm72016 ?s memory is partitioned according to the logical and ph ysical mapping shown in the table below . table 1: memory map dspi address gen - 2 memory bank gen - 2 address word pointer (ebv8) description 0x000 reserved 0x000 0x00 kill password[31:16] 0x001 reserved 0x001 0x01 kill password[15:0] 0x002 reserved 0x002 0x02 access password[31:16] 0x003 reserved 0x003 0x03 access password[15:0] 0x004 epc 0x000 0x00 crc 0x005 epc 0x001 0x01 pc 0x006 epc 0x002 0x02 epc - word 0 (msw) 0x007 epc 0x003 0x03 epc - word 1 0x008 epc 0x004 0x04 epc - word 2 0x009 epc 0x005 0x05 epc - word 3 0x00a epc 0x006 0x06 epc - word 4 0x00b epc 0x007 0x07 epc - word 5 (lsw) 0x00c epc 0x008 0x08 epc - read memory 0x00d epc 0x009 0x09 epc - read memory 0x00e service 0x00a 0x0a reserved 0x00f service 0x00b 0x0b reserved 0x010 tid 0x000 0x00 tid - word 0: x e201 0x011 tid 0x001 0x01 tid - word 1: x 6216 0x012 tid 0x002 0x02 tid - word 2: serial #1 0x013 tid 0x003 0x03 tid - word 3: serial #2 0x014 user 0x000 0x00 reserved 0x015 user 0x001 0x01 rfu 0x016 user 0x002 0x02 control/status register 0x017 user 0x003 0x03 working stored address register 0x018 user 0x004 0x04 0x019 user 0x005 0x05 0x01a user 0x006 0x06 user memory - start 0x01b user 0x007 0x07 0x0fe user 0x0ea 0x816a 0x0ff user 0x0eb 0x816b 0x100 user 0x0ec 0x816c 0x101 user 0x0ed 0x816d 0x1fe user 0x1ea 0x836a 0x1ff user 0x1eb 0x836b 0x200 user 0x1ec 0x836c 0x201 user 0x1ed 0x836d 0x3ba user 0x3a6 0x8726 0x3bb user 0x3a7 0x8727 16k memory: end (blk_size = 1 word/block) 0x3bc user 0x3a8 0x8728 0x3bd user 0x3a9 0x8729 0x3be user 0x3aa 0x872a
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 5 of 32 dspi address gen - 2 memory bank gen - 2 address word pointer (ebv8) description 0x3da user 0x3c6 0x8746 0x3db user 0x3c7 0x8747 16k memory: end (blk_size = 2 words/block) 0x3dc user 0x3c8 0x8748 0x3dd user 0x3c9 0x8749 0x3de user 0x3ca 0x874a 0x3ea user 0x3d6 0x8756 0x3eb user 0x3d7 0x8757 16k memory: end (blk_size = 4 words/block) 0x3ec user 0x3d8 0x8758 0x3ed user 0x3d9 0x8759 0x3ee user 0x3da 0x875a 0x3f3 user 0x3df 0x875f 16k memory: end (blk_size = 8 words/block) 0x3f4 user 0x3e0 0x8760 0x3f5 user 0x3e1 0x8761 0x3f6 user 0x3e2 0x8762 0x3f7 user 0x3e3 0x8763 16k memory: end (blk_size = 16 words/block) 0x3f8 user 0x3e4 0x8764 0x3f9 user 0x3e5 0x8765 16k memory: end (blk_size = 32 words/block) 0x3fa user 0x3e6 0x8766 0x3fb user 0x3e7 0x8767 (blk_size > 32 words/block) 0x3fc user 0x3e8 0x8768 reserved 0x3fd user 0x3e9 0x8769 reserved 0x3fe user 0x3ea 0x876a reserved 0x3ff user 0x3eb 0x876b reserved note: when accessing the memory through the dspi serial port, c are must be taken to ensure that reserved memory required to store critical parameters for the operation of the device is not altered. gen2 wm72016 memory banks the rfid memory banks reside in ramtron?s non - volatile f - ram memory. f - ram brings many benefits to the wm72016. the first benefit is the size of the memory itself C 16k - bit, most of which is available in the user memory bank. f - ram?s impact on the gen2 protocol is most dramatically seen when writing to wm72016 memory. unlike eeprom memory, no charge pump or memory soak time is required to write to wm72016 memory resulting in zero time and zero power penalties . the write cycle is completed immediately, allowing an interrogator to continue writing additional data to memory with no time penalty incurred due to the memory itself. a comparison between f - ram and eeprom memories is shown in figure 3 . the figure shows the minimum number of gen2 instructions required to perform a select, inventory, and access sequence of commands to write a data word to memory. the same interrogator command sequence is trans mitted to the wm72016 and a n eeprom - based rfid. the effect of the eeprom time penalty is shown within the context of the protocol.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 6 of 32 figure 3. gen2 memory write cycle comparison: f - ram vs. eeprom memories reserved: kill password : the kill password provides a mechanism to permanently disable the wm72016 rfid from responding to any and all gen2 interrogator commands. the mandatory kill command can be issued by a rfid interrogator in eith er t he open or secured states. the wm72016 is perm anently killed through a four - instruction sequence of reqrn and kill commands as detailed in the gen2 standard. the kill password is a 32 - bit value stored as 2 16 - bit data words in reserved memory. the most significant kill password is stored in reserved memory bank address 0x00 with the least significant word stored in reserved memory bank address 0x01. the kill function can be permanently disabled by setting both kill password words to 0x0000, and permanently locking the kill password in the reserved m emory bank. once the kill password has been set, it should be permanently locked using the lock command. the wm72016 is shipped from the factory with the k ill password memory unlocked. the kill state of the device only affects the gen2 rfid processor C the dspi serial port will continue to function normally. reserved: access password : the access password provides a security mechanism to prevent unauthorized rfid interrogators from writing to wm72016 memory. non - zero access passwords require the wm72016 be placed in the secured state prior to writing to it. this is accomplished through a four - instruction sequence of reqrn and access commands as described in the gen2 standard . an access password with a value of zero requires no authentication prior to w riting to wm72016 memory. the access passwo rd is a 32 - bit value stored as two 16 - bit data words in reserved memory. the most significant access password is stored in reserved memory bank address 0x02 with the least significant word stored in reserved mem ory bank address 0x03. once the access password has been set, it should be permanently locked using the lock command. the wm72016 is shipped from the factory with the access password memory unlocked. the value of the access password has no effect on the f unctionality of the dspi serial port. epc memory bank : the epc memory bank accommodates 8 words: 1 protocol control (pc) word, a 6 - word (96 - bit) memory space for an epc identifier, and a 1 - word crc. the crc word is calculated as part of the wm72016 powe r - on initialization routine and written into the epc memory bank address 0x00. the pc and 6 - word epc identifier are completely programmable. the protocol control field is shown in figure 4 . i n t e r r o g a t o r t a g m a x a r i a s w r i t e c y c l e q u r y ( 2 4 0 u ) s e l e c t ( 3 8 5 u ) a c k ( 1 7 5 u ) r e q r n ( 3 4 5 u ) e p c ( 2 2 8 u ) w r i t e ( 4 9 5 u ) r n ( 5 3 u ) h a n d l e ( 7 8 u ) w r _ o k ( 8 0 u ) r e q r n ( 3 4 5 u ) r n 1 6 ( 7 8 u ) e e p r o m w r i t e d e l a y ! c h a r g e p u m p & e e s o a k t i m e e e p r o m - b a s e d w r i t e c y c l e 4 m s
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 7 of 32 figure 4. epc protocol control word the five most significant bits of the pc indicates the size of the epc identifier in words C for a 96 - bit (6 - word) epc identifier, the pc should be programmed to 0b0011_0xxx_xxxx_xxxx. the len parameter of the pc word may not be greater than 0b00110 C a len parameter of 0b00000 has an epc identifier length of zero words resulting in only the pc and crc words when wm72 016 is acknowledged. the umi bit (user memory identifier) is asserted to a logic one by wm72016 and mapped to bit 10 of the pc word. in the event the host write s a logic zero to the umi bit, the memory location will be written with a logic zero, however the backscattered epc identifier will assert the umi bit to a logic one which is also used in the calculation of the crc. wm72016 does not support extended protocol control and should be written with a logic zero. pc word b its 8 down to 0 of the pc word are factory - initialized to zero . the wm72016 is shipped from the factory with the epc memory bank unlocked. tid memory bank : the tid memory bank consists of 4 words (64 bits), and is defined as shown in table 2 . the tid memory bank is permanently lock ed at the factory and obeys the iso/iec 15963 numbering convention. table 2: tid memory bank fields figure 5. tid memory bank fields bit field value (hex) description 00 h C 07 h e2 iso/iec 15963 class - identifier 08 h C 13 h 016 mask - designer identifier (mdid) C ramtron international 14 h C 1f h 216 tag model number 20 h C 3f h 32 - bit unique identifier 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 d e f a u l t n u m b e r i n g s y s t e m i d e n t i f i e r n s i t y p e e x t e n d e d p r o t o c o l c o n t r o l u s e r m e m o r y i d e n t i f i e r e p c i d e n t i f i e r w o r d l e n g t h l e n n s i x p c n t u m i 1 5 1 1 9 1 0 8 7 0 b i t p r o t o c o l c o n t r o l w o r d c l a s s i d e n t i f i e r m d i d [ 1 1 : 4 ] m d i d [ 3 : 0 ] t m n [ 1 1 : 0 ] i d [ 3 1 : 1 6 ] i d [ 1 5 : 0 ] 0 7 8 1 5 1 6 2 0 3 1 3 2 4 7 4 8 6 3 1 9
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 8 of 32 user memory bank : the user memory bank comprises two special - function control words, factory - reserved words, and up to 993 available memory locations. refer to table 1 for detail on the wm72016 memory structure. the user memory bank may be completely locked through the lock command. wm72016 also supports the blockpermalock command providing the ability to lock contiguous words of user memo ry, with word block sizes as small as a single word up to a maximum block size of 128 words. the user memory bank ships from the factory completely unlocked.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 9 of 32 tag - to - reader data encoding the wm72016 supports both encoding formats defined in the gen2 stand ard: ? fm0 baseband (fm0) ? miller modulation of a subcarrier (mms) data encoding is performed in the wm72016 as described in the gen2 standard. a fm0 data symbol is transmitted with period t which is defined by the tag - to - reader link frequency. the difference between a logic 0 and a logic 1 is defined by an additional mid - bit transition for a logic 0 as shown below in figure 6 . data encoding using miller modulation of a subcarrier (mms) is further defined by a rate parameter m that defines the number of link frequency cycles per data bit: 2, 4, or 8, resulting in data encoding defined as mms2, mms4, o r mms8 respectively. mms data encoding results in a phase inversion of the sub - carrier frequency when one of the following conditions occurs: ? at the mid - bit of a logic 1 data bit, or ? at the bit - boundary of two consecutive logic 0s. the following set of fo ur figures depicts the data bit values 00, 01, 10 and 11 for fm0 and mms data encoding formats. the same link frequency is shown for all cases, however the mms parameter m lengthens the baseband bit period by 2, 4, or 8 as shown in figure 7 , figure 8 , and figure 9 . figure 6. fm0 data encoding figure 7. mms2 data encoding figure 8. mms4 data encoding figure 9. mms8 data encoding 0 t 2 t 1 1 1 0 0 1 0 0 0 2 t 4 t 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 4 t 8 t 1 1 1 0 0 1 0 0 0 8 t 1 6 t
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 10 of 32 control / status register accessing the unique features of wm72016 is accomplished through the control/status register in f - ram non - volatile memory. the register is located at physical address 0x016 or user memory address 0x002. the control/status word register is organized as shown in table 3 below . care should be exercised when writing the control/status register word if it is to remain unlocked. figure 10. control/status register table 3: control/ status word register bit mnemonic function initial value 15 lock memory locking of this register. lock permalock description 0 0 register unlocked 0 1 register permanently unlocked 1 0 register writeable only from the secured state 1 1 register permanently locked 0 14 permalock 0 13 rfu reserved for future use 0 12 rfu reserved for future use 0 11 rfu reserved for future use 0 10 rfu reserved for future use 0 9 rfu reserved for future use 0 8 rfu reserved for future use 0 7 blkwren enables use of the custom command blockwrite. 1 6 blksiz [2] user memory block size. blksiz[2:0] # words blksiz[2:0] # words 000 1 100 16 001 2 101 32 010 4 110 64 011 8 111 128 1 5 blksiz [1] 1 4 blksiz [0] 0 3 wrpstat indicates if the working stored address has wrapped . logic state description 0 wrapping has not occurred 1 wrapping has occurred at least once 0 2 wrpen enables wrapping of the working stor ed address when it reaches the t op of l ogical m emory . logic state description 0 disable memory wrapping 1 enable memory wrapping. 0 1 autolock enable automatic locking of all user memory between the start of user memory and the working s tored a ddress register. logic state description 0 auto - lock disabled 1 auto - lock enabled 0 0 autoincr enable the working s tored a ddress word to a uto - increment when performing an unaddressed write cycle. logic state description 0 disable auto - increment of stored address register 1 enable auto - increment of stored address register 0 l c k p l c k r f u b w e n b l k s i z w r p w r p e n a l c k a i n c
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 11 of 32 upon power up, wm72016 ?s control logic reads the control word out of memory and configures itself accordingly. user applications may ch ange the control word as needed providing the register has not been permanently locked. the control/status word may be read by the application at any time. register locking : the lock a nd permalock control bits are implemented in a similar manner as locking bits used for gen2 memory bank locking with the exception that the lock control bits are incorporated into the register they are locking. as such, attention needs to be pla ced on how the contents of the c ontrol/ s tatus word are written when the register is not completely unlocked. table 4: control/status word locking lock perma - lock description 0 0 register unlocked. all control bits, including the lock and permalock bits can be written to from the open or secured states. 0 1 register permanently unlocked. all control bits can be written from the open or secured states. the lock and permalock bits must be set to logic values 0 and 1 respectively when writing the control/status word. 1 0 register locked. all control bits can be written to only from the secured state. the register cannot be written to in the open state. the lock and permalock bits must be set to logic values 1 and 0 respectively when writing the control/status word. 1 1 register permanently locked. the register cannot be written in any circumstance. block write enable : the blkwren control bit enables usage of the wm72016 custom command blockwrite. the blkwren parameter is internally updated during power - on wm72016 initialization. in the event the host application toggles the state of blkwren either through the gen2 or serial interfaces, a wm72016 power cycle is required to reflect the change. bl ock size : the 3 blksiz[2:0] control bits adjust the user memory block sizes as shown in table 5 . this provides a host application the ultimate flexibility in determining a balance between the user memory requirements and the granularity of the number of user memory words per block. the larger the granularity of the block size, the greater amount of available user memory. the effect of the block size on available user memory is shown in table 1 . the total number of user memory words available as a funct ion of the block size is shown in table 5 below . it is of utmost importance that the 3 - bit block size is not modified once set, which would otherwise result in corruption of block permalock status bits. table 5: available user memory memory blksiz words/block free user memory (words) 16k 000 1 931 16k 001 2 963 16k 010 4 979 16k 011 8 987 16k 100 16 991 16k 101 32 993 16k 110 64 993 16k 111 128 993 wrap status : the wrpstat status bit is asserted to a logic one when the following conditions are true: (a) wrpen =1 , autoincr=1 and autolock=0, (b) the contents of the working stored address register address the last user memory location, and (c) an unaddressed write command is received . the wr p stat can be cleared by the rfid interrogator by writing a logic zero to the wr p s tat bit.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 12 of 32 wrap enable : asserting the wrpen control bit to a logic one enables the user memory wrapping feature. the wrap enable feature allows the stored address pointer to wrap back to the factory - set initial stored address value of 0x006. in this manner, the wm72016 memory acts as a circular buffer. clearing the wrpen control bit disables wrapping resulting in a write - once memory. in this case, when the w orking s tored a ddress reaches the end of user memory, no additional unaddressed write cycles will be possible. the wrpen and autolock control bits are mutually exclusive C only one of the two control bits may be asserted at any given time. auto lock enable : asserting the autolock control bit to a logic one enables memory locking of the u ser memory span between the start of user memory and the w orking s tored a ddress . the autolock and wrpen control bits are mutually exclusive C only one of the two control bits may be asserted at any given time. the automatic locking feature can only be us ed when autoincr is asserted to a logic one. auto increment : asserting autoincr control bit to a logic one enables the working s tored a ddress increment function. upon receiving an unaddressed write cycle, the wm72016 increments the pointer stored in the working stored address register to point to the next free memory location then writes the cover - coded data word to the respective memory location . this functionality removes any requirement for a rfid interrogator to determine where free user memory is located and manipulating the memory pointer itself. working stored address to better utilize the f - ram?s fast write capability, memory has been architected using an optional w orking s tored a ddress register . the stored address function enables automation o f the storage of large blocks of user data, such as pe digree or tracking information. this feature enables a rfid interrogator the ability to use a standard gen2 write command using a designated address of 0x3fff ( 0xff7f ebv - formatted ) as a redirect point er to use the contents of the w orking s tored a ddress register C this is referred to as an unaddressed write (unaddr_write) . the working stored address is a user memory address pointer used to address the first available user memory data word as shown in f igure 12 . the w orking s tored a ddress is a read/write register located at address 0x003 in user memory . it may be used to address user memory only C it is an address pointer to a memory location within the user memory bank and cannot be used to address other memory banks or memory regions in the wm72016. it may be manually updated by simply writing to user memory address 0x003 or will automatically increment when the autoincr control bit in the control/status register is asserted to a logic one and an unaddressed write command is received . figure 11. working stored address register table 6: working stored address C bit definitions bit mnemonic function initial value 15 lock memory locking of this register. lock permalock description 0 0 register unlocked 0 1 register permanently unlocked 1 0 register writeable only from the secured state 1 1 register permanently locked 0 14 permalock 0 13 :11 rfu reserved for future use 0 10 initen when asserted to a logic 1, sets the contents of the initial stored address register with the value defined in the 10 - bit address field in bits 9 through 0 written to this register using a gen2 write instruction. 0 9 :0 addr working stored address pointer 006 l c k i n i t e n r f u a d d r [ 9 : 0 ] p l c k
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 13 of 32 working stored address pointer gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x0006 user 0x004 user 0x005 ? ? user 0x006 user memory - start available memory user 0x007 user 0x008 user user user memory - end figure 12. user memory bank: working stored address register the syntax for an unaddressed write command is shown in figure 13 below . all protocol requir ements governing implementation of a write command also apply to the unaddr_write command. figure 13. unaddressed write syntax upon reception of a valid unaddr_write command, the wm72016 examines the state of the autoincr control bit : autoincr=0 : the 16 - bit data word cover - coded in the unaddressed write instruction is written to the memory address stored in the working stored address register. the contents of the working stored address register remain unaltered. to avoid the memory be ing over - written, the working stored address register must be manually updated. autoincr=1 : the working stored address register is incremented by one, followed by the 16 - bit data word being written to memory. the contents of the working stored address r egister will reflect the memory address just written to. a single unaddressed write cycle is shown in figure 14 with the autoincr control bit set to a logic one. the working stored address has an initial value of 0x0006 as shown in figure 12 . an unaddres sed write cycle (with autoincr=1) increments the address pointer to 0x0007 followed by a write cycle to the wm72016 memory resulting in data word data 0 being written to user memory address 0x007. figure 15 depicts an additional seven discrete unaddressed write cycles (reqrn command for cover - coding not shown). prior to unaddressed write commands, the working stored address has a memory address of addr n . an unaddressed write command with data payload data n is written to addr n+1 ; the following unaddressed write command with data payload data n+1 is written to addr n+2 , and so on. upon completion of the final unaddressed write command, the memory pointer contents of the working stored address will be addr n+8 , reflecting the memory address of the last unaddres sed write cycle. in this manner, the rfid interrogator does not have to read the memory contents to discern the next available memory location . this substantially reduces the time required in the rf field yielding greater throughput of a population of ta gs . the working stored address pointer will be factory - initialized to the start of user memory then managed by the memory controller or the host application as required. w r i t e ( 0 x c 3 ) m e m b a n k ( 0 b 1 1 ) w o r d p t r ( 0 x f 7 f f ) 1 6 - b i t d a t a ( c o v e r - c o d e d ) ( 0 x n n n n ) h a n d l e ( 0 x h h h h ) c r c - 1 6 ( 0 x c c c c )
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 14 of 32 working stored address pointer gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x0007 user 0x004 user 0x005 ? user 0x006 user memory - start available memory ? ? user 0x007 unaddr_write: data0 user 0x008 user user user memory - end figure 14. single unaddressed write cycle , autoincr=1 working stored address pointer gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x000e user 0x004 user 0x005 ? user 0x006 user memory - start available memory ? user 0x007 unaddr_write: data0 ? user 0x008 unaddr_write: data1 user 0x009 unaddr_write: data2 user 0x00a unaddr_write: data3 user 0x00b unaddr_write: data4 user 0x00c unaddr_write: data5 user 0x00d unaddr_write: data6 ? ? user 0x00e unaddr_write: data7 user 0x00f user 0x010 user 0x011 user memory - end figure 15. multiple unaddressed write cycles, autoincr=1
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 15 of 32 initial stored addre ss the initial stored address is a preset address pointer that is loaded into the working stored address when a memory wrap occurs after an unaddressed write command is executed. a memory wrap only occurs if the wrpen control bit is asserted to a logic one and the autolock control bi t is cleared to a logic zero in the control/status register and the working stored address points to the last free memory location in the user memory bank (last memory location depends on the set block size). the contents of the initial stored address may be altered by setting the initen bit to a logic one through a gen2 write cycle to the working stored address register C refer to table 6 above . when the initen control bit is set during a write cycle, the contents of the working stored address regist er in user memory 0x003 are not affected. use of an initial stored address register provides flexibility when using the wrap enable feature of wm72016. it may be set to the start of user memory, allowing the entire user memory bank to be utilized. altern atively, it may be set to a higher memory address within the user memory bank. this mechanism would provide for a static user memory bank and a dynamic user memory bank as shown in figure 16 below . in the example shown in figure 16 , the working stored address points to address 0x3f8 after having written user_log_data[ n ] w ith an unaddressed write command. the subsequent unaddressed write cycle will increment (wrap) the working stored address to the value defined by the initial stored address , defined in this example as 0x000a, and write the value user_log_data[ n +1] to user memory bank 0x00a, over - writing the previous data contents user_log_data[0]. in the example shown, four memory locations are used for static memory, or memory that will not be over - written when a wrap condition has occurred.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 16 of 32 working stored address poi nter gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x03f8 user 0x004 user 0x005 ? user 0x006 user_static_data0 static ? user 0x007 user_static_data1 ? user 0x008 user_static_data2 user 0x009 user_static_data3 initial stored address user 0x00a user_log_data[0], user_log_data[ n +1] dynamic user 0x00b user_log_data[1] user 0x00c user 0x00d ? user 0x00e user 0x00f user 0x010 user 0x011 user 0x3f7 user_log_data[ n - 1] ? ? user 0x3f8 user_log_data[ n ] figure 16. initial stored address example C block size = 128 words/block the initial stored address is factory - initialized with a value of 0x0006 (user memory bank address 0x006).
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 17 of 32 supported commands the wm72016 supports the following select, inventory, and access commands as described in the epcglobal class 1 generation 2 uhf rf id specification . please refer to the r eferenced document for detailed descriptions of these commands. ? select ? query ? queryadjust ? queryrep ? ack ? nak ? req_rn ? read ? write ? kill ? lock ? access ? blockwrite * ? blockpermalock maxarias gen2 custom command: bloc kwrite t he wm72016 supports a customized version of the blockwrite command to support unique features within the device. the blockwrite command optional feature is enabled by asserting the blkwren control bit in the control/status register to a logic one, after w hich the wm72016 will require a power cycle to initialize itself. to support other features within the wm72016, the blockwrite command uses the address stored in the working stored address register. the address pointer passed in the blockwrite command is the physical address 0x3fff (ebv formatted address = 0xf7ff), representing the same address used for unaddressed write cycles. a single blockwrite command carries a maximum data payload of 127 words. blockwrite commands with data payloads greater than 1 27 words may optionally be written to unlocked memory, however wm72016 will not acknowledge the blockwrite command with a success message. in this event, the host interrogator may perform one or more read cycles to verify user memory data content s. prior to transmitting a blockwrite command, the interrogator must set the working stored address register through a standard gen2 write command. the blockwrite command is shown in figure 17 below . figure 17. block write syntax b lockwrite commands do not support the auto - increment feature used for unaddr_write commands. as such, the working stored address must be manually updated by the host interrogator and will not be altered by a blockwrite command. when using the streaming capabilities of the blockwrite command, care should be taken to consider the logic state of the autoincr control bit. as with una ddr_write commands, the working stored address register is incremented prior to writing data to memory when autoincr=1 affecting the first u ser memory address written to. figure 18 shows an 8 - word blockwrite command with autoincr=0; figure 19 shows a blockwrite command with autoincr=1. in the respective figures, when autoincr=0, data is written starting at the address defined by the working stored address register C 0x006; when autoincr=1, data is written starting at the next free address defined by the contents of the working stored address incremented by one, or 0x007. it is important b l k w r i t e ( 0 x c 7 ) m e m b a n k ( 0 b 1 1 ) w o r d p t r ( 0 x f 7 f f ) d a t a ( x n n 1 6 - b i t d a t a ) h a n d l e ( 0 x h h h h ) c r c - 1 6 ( 0 x c c c c ) w o r d c n t ( 0 x n n )
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 18 of 32 to note that in both cases, the value stored in the working stored address register does not change for a blockwrite command C in the example shown, it remains at a value of 0x006 . working stored address pointer gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x0006 user 0x004 user 0x005 ? ? user 0x006 blkwrite: data0 available memory ? user 0x007 blkwrite: data1 ? user 0x008 blkwrite: data2 user 0x009 blkwrite: data3 user 0x00a blkwrite: data4 user 0x00b blkwrite: data5 user 0x00c blkwrite: data6 user 0x00d blkwrite: data7 ? user 0x00e user 0x00f user memory - end figure 18. blockwrite command: autoincr=0 working stored address pointer gen - 2 memory bank gen - 2 address description reserved 0x000 - 0x003 reserved - passwords memory unavailable epc 0x000 - 0x009 epc service 0x00a reserved service 0x00b reserved tid 0x000 - 0x003 tid user 0x000 reserved user 0x001 rfu user 0x002 control/status register user 0x003 working stored address register: 0x0006 user 0x004 user 0x005 ? ? user 0x006 user memory - start available memory ? user 0x007 blkwrite: data0 ? user 0x008 blkwrite: data1 user 0x009 blkwrite: data2 user 0x00a blkwrite: data3 user 0x00b blkwrite: data4 user 0x00c blkwrite: data5 user 0x00d blkwrite: data6 ? user 0x00e blkwrite: data7 user 0x00f user memory - end figure 19. blockwrite command: autoincr=1
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 19 of 32 dual serial peripher al interface (dspi) the wm72016 employs a dual serial peripheral interface (dspi) bus providing a serial communication port to a host microcontroller for the purpose of directly reading and writing memory. the interface uses four pins as shown in table 7 . table 7: dspi interface signal name direction description cs input/output chip select d1 input/output data bit 1 d0 input/output data bit 0 clk input clock a single dspi access cycle is composed of a 16 - bit instruction word and a 16 - bit data word as shown in figure 20 . a dspi read/write cycle is initiated by asserting cs high followed by 16 clock cycles. the host drives the first set of 8 clock cycles to write 2 data bytes comprising an instruction word C the second set of 8 clock cycles are required for the 16 - bit data word. command and data bits are interleaved across two dspi data signals in such a manner that odd numbered bits are driven on one data signal while even numbered bits are driven on the other data signal as shown in section dspi serial port timing . this results in a 16 - bit word transfer on the d0 and d1 signals every 8 clock cycles . figure 20. dspi cycle write cycles d spi write cycles are detailed in the dspi serial port timing section. the h ost microcontroller drives all four dspi signals for the duration of the cycle. the wm72016 uses the rising edge of clk to shift in the 2 data bits presented on the d1 and d0 sign als. the host microcontroller shall obey the timing constraints detailed in table 10 . the host microcontroller asserts the 2 data bits prior to the rising edge of clk. the host microcontroller shifts the instruction word with the first set of 8 clk cycl es and shifts the data word on the second set of 8 clk cycles. the write cycle is terminated by clearing the cs signa l. read cycles spi read cycles are detailed in the dspi serial port timing section. the host microcontroller shall transmit the instruct ion word in the same manner as done for dspi write cycles. the wm72016 uses the rising edge of clk to shift in the 2 data bits presented on the d1 and d0 signals. once the instruction word has been completely transmitted and the clk signal has been clear ed to a logic zero, the host shall tri - state the d1 and d0 signals allowing the wm72016 to drive the data bits for the remainder of the read cycle. the wm72016 shall shift a pair of data bits on d1 and d0 on the rising edge of clk C the host shall use the falling edge of clk to capture the data pair into its shift register. the host shall transmit a total of 8 clk cycles to receive the entire data word, after which it clears the cs to a logic zero to terminate the read cycle. the syntax of the instructio n word is detailed in table 8 . i n s t r _ w o r d i n s t r _ w o r d d a t a _ w o r d d a t a _ w o r d c s c l k d 0 d 1
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 20 of 32 table 8: dspi instruction word signal mnemonic bit description read/write rw 15 read/write control. rw is asserted to logic ?1? for a read cycle. rw is cleared to logic ?0? for write cycle. opcode op 14..10 instruction opcode. address a 9..0 maxarias physical memory address. the read/write bit (rw) sets the data direction of the subsequent data word(s). on write cycles, the host continues to drives the dspi bus with data words. the maxarias wm72016 uses the rising edge of cl k to register data presented on d0 and d1. on read cycles, the host drives the dspi bus with the instruction word, then tri - states the d0 and d1 signals while receiving data from maxarias memory. the opcode (op) parameter is a 5 - bit value that can take on the following values shown in table 9 . table 9: dspi opcode values mnemonic opcode [4:0] description norm 11001 normal read/write instruction. intend 11101 interrupt end instruction. - others reserved two instruction opcodes available in the wm72016 are: 1. norm C normal opcode for all read/write instructions, and 2. intend C dspi serial port control register opcode. the address parameter of the dspi instruction word is a 10 - bit value capable of addressing the entire wm72016 1024 - word physical memory. physical memory addressing is shown in the left - most column in table 1 . in the event that memory arbitration is required between the rfid and serial interfaces, the rfid interface will always have priority. the only exception to this rule is wm72016 interrupt ge neration, during which time the serial port has full control over the memory. care needs to be taken to ensure that reserved memory required to store critical parameters for the operation of the device are not altered . dspi data streaming data may be str eamed into the wm72016 (write cycles) or out of wm72016 (read cycles) using a single instruction word and 2 or more consecutive data words as shown in figure 21. the example shown in the figure depicts n+1 data words. the host microcontroller initiates th e read or write instruction in the same manner as detailed earlier: the cs signal is asserted, followed by 8 clk cycles to shift the instruction word and 8 clk cycles to shift the data word. from this point forward, each set of 8 clk cycles is used to rea d or write the next wm72016 memory location. while the cs signal remains at a logic one, the wm72016 automatically increments an internal address pointer after every data word cycle has completed. the state of the autoincr bit in the control/status regis ter and the contents of the working stored address have no impact on dspi data streaming. likewise, autoincr and the working stored address register are not affected by dspi serial port data streaming. the data streaming cycle is terminated once cs has b een cleared to a logic zero. the dspi streaming capability removes the requirement for multiple instruction words, greatly improving bandwidth requirements.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 21 of 32 figure 21. dspi write cycle detail note: in the event of a simultaneous memory access, the rfid request will take priority over the secondary dspi serial interface. microcontroller inte rrupts the wm72016 is capable of generating interrupts initiated by a rfid interrogator to a microcontroller on the serial port. interrupt generation provides a mechanism to alert a host microcontroller that a rfid interrogator is present and to take control of the memory with no possibility of interruption from the rfid interface. during an interrupt, all rfid commands are disregarded until an intend dspi command is received to terminate the interrupt and return control back to the rfid interface. an interrupt is generated from the wm72016 to the host by writing two standard gen2 write cycles to user memory addresses 0x004 and 0x005. the xor operation of the two data words written to the two respective addresses must equal 0x1234. as with all gen2 write commands, the wm72016 must be in the open or secured state prior to executing the write command sequence. should the wm72016 rfid have a non - zero access password, the device must be transitioned to the secured state by correctly accessing the tag with the device?s access password. the rfid interrogator then transmits two cover - coded write commands to user m emory addresses 0x004 and 0x005 whose two data words when xored together result in a value of 0x1234. a correct sequence of the write commands will result in the wm72016 asserting an interrupt by driving the dspi cs high. upon detection of a high state o n the cs signal, the host microcontroller drives two clock cycles on the dspi clk to acknowledge and clear the wm72016 interrupt. the host microcontroller now has full and uninhibited access to the wm72016 memory. any attempted access by a rfid interroga tor during this period will be disregarded until one of two conditions has occurred : ? the host microcontroller has released control of the wm72016 memory by writing an instruction with the intend opcode, or ? the wm72016 has been power - cycled. the entire in terrupt generation sequence is shown in figure 22 . note that the values x1200 and x0034 shown in figure 22 are shown for illustration purposes only C any two values whose xor operation results in a value of x1234 will generate a dspi interrupt. the host microcontroller releases its control of the wm72016 memory by writing a n instruction with an intend opcode refer to table 9 . the contents of the dspi write data word payload that follows the instruction word are ignored but must be present to constitute a valid dspi command. note: should the outcome of two write cycles to u ser memory locations 0x004 and 0x005 result in a xor value that is not 0x1234, the interrupt mechanism will be disabled until the wm72016 has been power - cycled. in this case, the two memory locations may be used as standard user memory, however any future use of these memory locations may potentially generate an unintended interrupt C as such, it is not recommended to use these memory locations as part of the standard user memory bank. t w d t c s h t h d t c l k t s u t c s d d 1 4 d 1 2 d 1 0 d 8 d 6 d 4 d 2 d 0 o p 4 o p 2 o p 0 a 8 a 6 a 4 a 2 a 0 d 1 5 d 1 3 d 1 1 d 9 d 7 d 5 d 3 d 1 w r o p 3 o p 1 a 9 a 7 a 5 a 3 a 1 c s d 0 d 1 c l k
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 22 of 32 figure 22. gen2 interrupt generation c s c l k g e n 2 g e n e r a t e d i n t e r r u p t d 1 d 0 r e q r n r n 1 6 w r i t e w r o k r e q r n r n 1 6 w r i t e w r o k r n 1 6 = x p p p p w o r d p t r = 0 x 0 0 4 ; d a t a = x p p p p x o r x 1 2 0 0 r n 1 6 = x q q q q w o r d p t r = 0 x 0 0 5 ; d a t a = x q q q q x o r x 0 0 3 4 g e n 2 i n t e r r o g a t o r t x w m 7 2 0 1 6 b a c k s c a t t e r t x w m 7 2 0 1 6 r f i d g e n 2 i n t e r f a c e w m 7 2 0 1 6 d s p i i n t e r f a c e c s a s s e r t e d b y w m 7 2 0 1 6
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 23 of 32 specifications wm72016 ?s rfid interface conforms to the specification for rfid air interface epc class - 1 generation - 2 uhf rfid protocol for communications at 860 mhz C 960 mhz, version 1.2.0 . options and exceptions are noted here: state persistence requ irements wm72016 features i nfinite state retention for s1, s2, s3, and sl state f lags. state flag s0 has no persistence and will always return to state ?a? upon a power cycle. electrical specifica tions a bsolute m aximum r atings symbol description ratings notes v ddr , v ddraw power supply voltage with respect to ant - - 1.0v to +4.5v v in voltage on any serial port pin with respect to ant - - 1.0v to +4.5v and v in < v dd +1.0v t stg storage temperature - 55 ? c to + 125 ? c t op operating temperature - 40 o c to +85 o c t lead lead temperature (soldering, 10 seconds) 260 ? c v esd (ant+, ant - ) electrostatic discharge voltage - human body model (jedec std jesd22 - a114 - b) - charged device model (jedec std jesd22 - c101 - a) - machine model (jedec std jesd22 - a115 - a) 500v 1kv 50v v esd (all other pins) electrostatic discharge voltage - human body model (jedec std jesd22 - a114 - b) - charged device model (jedec std jesd22 - c101 - a) - machine model (jedec std jesd22 - a115 - a) 1.5kv 1.5kv 200v me memory endurance: read or write or erase 1x10 1 4 1 rf exp rf exposure +10dbm ( 800 ~ 1000 mhz ) package moisture sensitivity level msl - 2 1. a degradation in memory endurance may occur for vddr_ext levels beyond the maximum specification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 24 of 32 rf operating characteristics ( t a = - 40 ? c to + 85 ? c unless otherwise specified) symbol parameter min typ max units notes s r read sensitivity - 6 dbm s w write sensitivity - 6 dbm fr max sustainable read rate @ s r 640 kbits/s 1 fw max sustainable write rate @ s w 160 kbits/s 1 t st power - on time 1.0 1.5 ms ??? change in m odulator r eflection c oefficient tbd tbd z in input impedance @ f in =915 mhz 63 C j199 ohms 2 note: 1. actual read & write speeds are constrained by the epc class 1 gen2 data communication standard. 2. z in is measured at s r /s w .
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 25 of 32 dspi serial port tim ing figure 23. dspi power supply timing figure 24. dspi write cycle detail figure 25. dspi read cycle detail s e r _ c l k i n s t r _ w o r d d a t a _ w o r d s e r _ d 1 i n s t r _ w o r d d a t a _ w o r d s e r _ d 0 s e r _ c s t p s u t p h v d d r t w d t c s h t h d t c l k t s u t c s d d 1 4 d 1 2 d 1 0 d 8 d 6 d 4 d 2 d 0 o p 4 o p 2 o p 0 a 8 a 6 a 4 a 2 a 0 d 1 5 d 1 3 d 1 1 d 9 d 7 d 5 d 3 d 1 w r o p 3 o p 1 a 9 a 7 a 5 a 3 a 1 c s d 0 d 1 c l k d 1 4 d 1 2 d 1 0 d 8 d 6 d 4 d 2 d 0 o p 4 o p 2 o p 0 a 8 a 6 a 4 a 2 a 0 d 1 5 d 1 3 d 1 1 d 9 d 7 d 5 d 3 d 1 r d o p 3 o p 1 a 9 a 7 a 5 a 3 a 1 c s d 0 d 1 c l k t d d
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 26 of 32 dspi serial port dc characteristics ( t a = - 40 ? c to + 85 ? c unless otherwise specified) symbol parameter min typ max units notes v dd r , v ddraw power s upply pins 2.1 2.5 3.0 v 1 i dd power supply operating c urrent 15 25 a v il input low v oltage - 0.3 0.3 v ddr v v ih input h igh v oltage 0.7 v ddr v ddr +0.3 v v ol output low v oltage - 0.3 v v oh output high v oltage v ddr - 0.3 - v notes: 1. measured at the pin. dspi serial port a c characteristics ( t a = - 40 ? c to + 85 ? c , v dd = 2.1v to 3.0v unless otherwise specified) symbol parameter min typ max units notes t psu vddr setup t ime 1.5 - ms t ph vddr hold t ime 0 - ns t csd chip select setup to data valid t ime 10 - ns t csh chip select hold t ime 10 - ns t su data setup t ime 10 t clk /2 - 10 ns t hd data hold t ime 10 - ns t dd read data valid t ime 600 ns t clk clock p eriod 1.6 - s t wd instruction to d ata w ord t iming t clk /2 - t ack interrupt acknowledge setup t ime 10 - ns
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 27 of 32 user memory block si ze definition x 0 0 0 x 0 0 1 x 0 0 2 x 0 0 3 x 0 0 4 x 0 0 5 x 0 0 6 x 0 0 7 x 0 0 8 x 0 0 9 x 0 0 a x 0 0 b x 0 0 c x 0 0 d x 0 0 e x 0 0 f x 0 1 0 x 0 1 1 b l k : 0 b l k : 1 b l k _ s i z = 1 1 1 b l k : 0 b l k _ s i z = 1 1 0 b l k : 0 b l k : 1 b l k _ s i z = 1 0 1 b l k : 0 b l k : 1 b l k _ s i z = 1 0 0 b l k : 0 b l k : 1 b l k : 2 . . . b l k _ s i z = 0 1 1 b l k : 0 b l k : 1 b l k : 2 b l k : 3 b l k : 4 . . . b l k _ s i z = 0 1 0 b l k : 0 b l k : 1 b l k : 2 b l k : 3 b l k : 4 b l k : 5 b l k : 6 b l k : 7 b l k : 8 . . . b l k _ s i z = 0 0 1 b l k : 0 b l k : 1 b l k : 2 b l k : 3 b l k : 4 b l k : 5 b l k : 6 b l k : 7 b l k : 8 b l k : 9 b l k : 1 0 b l k : 1 1 b l k : 1 2 b l k : 1 3 b l k : 1 4 b l k : 1 5 b l k : 1 6 b l k : 1 7 b l k _ s i z = 0 0 0 . . . u s e r m e m o r y a d d r e s s x 0 1 3 x 0 1 2 x 0 1 4 x 0 1 7 x 0 1 8 x 0 1 f x 0 2 0 x 0 3 f x 0 4 0 x 0 7 f x 0 8 0 x 0 f f x 1 0 0 . . . . . . . . . . . . . . . . . . b l k : 1 . . . . . . . . . . . .
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 28 of 32 circuit example the wm72016 may be implemented in a manner similar to that shown below. notes: 1. rf performance of wm72016 is heavily dependent on matching impedance on the antenna port ant+/ - . 2. external voltage vddr_ext may be applied to vddraw to externally power the wm72016. vddr_ext must comply with specifications given in the dc characteristics of t his datasheet. 3. in some cases, additional bus termination may be required on the wm72016 end of the dspi serial bus. this is dependent on a number of factors, including bus length, bus impedance, connectors, processor drive voltage, i / o port drive strength , and i / o slew rate. excessive ringing on the bus may generate voltages beyond specifications causing unpredictable performance characteristics. w m 7 2 0 1 6 c l k d 1 d 0 c s v d d r a n t + a n t - v d d r _ e x t p g n d i / o i / o i / o i / o b u s t e r m i n a t i o n m a y b e r e q u i r e d v d d r a w m a t c h i n g n e t w o r k
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 29 of 32 specification & comp liance summary refer to epc tm radio - frequency identity protocols class - 1 generation - 2 uhf rfid protocol for communications at 860mhz - 960mhz version 1.2.0 for all critical rfid specifications. link to specifications page: http://www.epcglobalus.org/standards/epcglobalspecifications/tabid/335/default.aspx
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 30 of 32 mechanical drawings 8 - pin u dfn (3.0 mm x 3.0 mm body, 0.65 mm pad pitch) note: all dimensions in millimeters . c are must be taken to ensure pcb traces and vias are not placed within the exposed metal pad area. udfn p ackage m arking s cheme for b ody s ize 3 mm x 3 mm legend: xxxxxxx= base part number (wm72016) llllllll= lot code r=revision, p=package (d=dfn), n=split designator (numeric) ric=ramtron int?l corp, yy=year, ww=work week example: wm72016, green udfn - 8 package, lot 0411702, rev b., year 2010, work week 12 wm72016 0411702 bd1 ric1012 xxxxxxxx llllllll rpn ricyyww
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 31 of 32 ordering information note: contact ramtron for other ordering options, i.e. bumped die. product description delivery & moq wm72016 - 6 - dg tr 8 - pin udfn with 16kb memory and dspi serial interface tape & reel C 3000 units
wm72016 C secure f - ram with gen - 2 rfid and serial port rev. 1.4 may 2011 page 32 of 32 revision history revision date summary 0.1 12/12/2008 initial release. 0.2 2/11/2009 order information and package update 0.3 3/7/2010 documentation updates 1.0 3/12 /2010 changed to preliminary status. 1.1 8/23/2010 changed read/write sensitivity specs. 1.2 9/7/2010 changed input impedance and the test frequency . 1.3 4/11 /2011 documentation updates and clarifications. 1.4 5/25/2011 modified memory map table on p. 5 ( changed line entr ies for dspi address 0x 3fa C

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